The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20 nm node). As the demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and latency has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies evolve, multiple chip wafer level package based semiconductor devices have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a wafer level package based semiconductor device, active circuits such as logic, memory, processor circuits and the like are fabricated on different wafers and each wafer die is stacked on top of another wafer die using pick-and-place techniques. Much higher density can be achieved by employing multiple chip semiconductor devices. Furthermore, multiple chip semiconductor devices can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption.
A multiple chip integrated circuit (IC) may comprise a top active circuit layer, a bottom active circuit layer and a plurality of inter-layers. Two dies may be bonded together through suitable bonding techniques. The commonly used bonding techniques include direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding and the like.
Eutectic bonding is a commonly used low temperature bonding technique for semiconductor vertical integration. During a eutectic bonding process, eutectic bonding materials such as aluminum, germanium and the like are deposited on the bonding sides of two wafers respectively through a suitable deposition process such as sputtering. One wafer is stacked on top of another wafer. The stacked wafers are placed in a chamber. The chamber temperature is elevated to a level, at which a eutectic reaction occurs and a eutectic alloy is generated between two wafers. Such a eutectic alloy not only generates a reliable bond between two wafers, but also provides a conductive channel between two wafers.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.